Lead ASIC DFT Engineer
This is the employer's own posting, not a copy on a job board.
What we know
Is it still open?
Confirmed still open
Last checked 20h ago — checked against the employer's own applicant tracking system, which is the company answering directly.
We re-read the employer's own applicant tracking system and the posting was still there. That is the company answering directly.
How old is it?
Posted 55d ago
The date the source published, not the day we noticed it (2026-07-22). Last seen at its source 1h ago.
Is it remote?
Marked remote on the employer's board
Their board carries a remote setting on this posting — a field they filled in, not wording we read. The location field names somewhere specific, which is usually where the team or the entity sits.
Who may apply?
United States
The description states no restriction of its own. This is the source's own tag.
Pay not stated
Similar roles pay $195.4k–255.4k/yr
Middle 50% of 552 listings that do state pay — Engineering · Lead · United States · USD/year. This employer has published no salary; this is what comparable listings we hold disclose, never converted between currencies or periods. How this is calculated.
Carried by 1 source
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workable employer's own board first seen 11d ago · last seen 1h ago
The listing
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.
The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield
Requirements
Required Skills & Qualifications
- Strong hands-on experience in ASIC DFT with end-to-end ownership.
- Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
- Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
- Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
- Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
- Experience with MBIST implementation and verification; SMS experience preferred.
- Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
- Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
- Proven post-silicon debug and silicon bring-up experience.
- Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
- Strong communication skills and the ability to work independently with minimal ramp-up.