RTL Design Engineer
This is the employer's own posting, not a copy on a job board.
What we know
Is it still open?
Confirmed still open
Last checked 1d ago — checked against the employer's own applicant tracking system, which is the company answering directly.
We re-read the employer's own applicant tracking system and the posting was still there. That is the company answering directly.
How old is it?
First seen 15d ago
No source stated a posting date, so this is when the listing first reached us — which is a floor, not the real age. Last seen at its source 5h ago.
We have tracked this listing since 18 Oct 2026 (15 days). The employer's own board has carried it every time we have read it, most recently 5 hours ago.
Is it remote?
Remote
That is the location the employer filed this posting under. Quoted as written — we do not re-word the source's own location.
Who may apply?
Not stated
The description states no restriction of its own. This is the source's own tag.
Carried by 1 source
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JazzHR employer's own board first seen 15d ago · last seen 5h ago
The listing
Overview
Inabia is seeking an RTL Design Engineer for a fully remote 12-month contract engagement focused on custom silicon development. The ideal candidate will own the full micro-architecture and RTL design lifecycle for complex digital blocks, operating independently from day one. This role requires hands-on fluency in SystemVerilog and recent experience with memory controller design and SoC integration.
Responsibilities
- Own micro-architecture definition derived from high-level functional specifications
- Develop and implement RTL for complex digital blocks using SystemVerilog/Verilog
- Drive digital block control logic and IP integration
- Participate in subsystem-level architecture alignment discussions
- Support design sign-off activities including CDC, RDC, lint, and synthesis readiness checks
- Collaborate closely with Design Verification (DV) teams for closure and debug
- Take full project lifecycle ownership with minimal supervision
Key Qualifications
- Strong, current expertise in RTL design using SystemVerilog and/or Verilog
- Demonstrated ability to independently define micro-architecture from functional specs
- Recent hands-on experience designing custom RTL blocks such as controllers, DMAs, or SoC bus bridges
- Solid understanding of memory controllers, including HBM, DDR4, or DDR5
- Experience with SoC integration and digital subsystem design
- Proficiency with IP integration and block-level ownership
- Working knowledge of sign-off flows including CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing)
- Experience designing IPs with multiple clock domains
- Ability to operate independently with no ramp-up time required
Preferred Qualifications
- Experience in subsystem-level RTL development
- Exposure to Die-to-Die (D2D) logic design
- Prior experience working directly with major hyperscaler silicon teams