Analog Layout Engineer
This is the employer's own posting, not a copy on a job board.
What we know
Is it still open?
Confirmed still open
Last checked 1d ago — checked against the employer's own applicant tracking system, which is the company answering directly.
We re-read the employer's own applicant tracking system and the posting was still there. That is the company answering directly.
How old is it?
Posted 2d ago
The date the source published, not the day we noticed it (2026-11-04). Last seen at its source 7h ago.
We have tracked this listing since 4 Nov 2026 (1 days). The employer's own board has carried it every time we have read it, most recently 7 hours ago.
Is it remote?
Remote, TX
That is the location the employer filed this posting under. Quoted as written — we do not re-word the source's own location.
Who may apply?
United States
The description states no restriction of its own. This is the source's own tag.
Pay not stated
Similar roles pay $155k–225.9k/yr
Middle 50% of 5282 listings that do state pay — Engineering · all levels · United States · USD/year. This employer has published no salary; this is what comparable listings we hold disclose, never converted between currencies or periods. How this is calculated.
Carried by 1 source
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JazzHR employer's own board first seen 1d ago · last seen 7h ago
The listing
Hello,
Job Title : Analog Layout Engineer
Client: Arrow Electronics
Experience Required: 7+ years (Relevant)
Work Location: Austin ,TX (Remote)
Visa: All visa, except H1B transfer
C2C engagements are allowed.
TSMC 4NM (Must Have)
High-Speed Analog Layout Engineer designs the physical silicon layout for high-frequency or high-speed mixed-signal circuits (such as SerDes, ADCs, DACs, PLLs, and High speed blocks).
Floor Planning & Integration: Create block-level and chip-top-level floor plans, manage hierarchical block integration, and handle micro-bump or package-aware co-design
Parasitic & Noise Control: Address layout-dependent effects (LOD, WPE, LDE), device matching, common-centroid structures, guard rings, and isolation or shielding (coaxial, differential, ground shields). [1, 2, 3]
Reliability & Verification: Ensure complete closure on DRC (Design Rule Check), LVS (Layout Versus Schematic), ERC, antenna rules, EM/IR (Electromigration / Infrared drop) reliability, and ESD protection
Generally 5 to 12+ years of hands-on custom IC layout experience in deep sub-micron or advanced CMOS/FinFET nodes (such as TSMC N3, N5, N7)
Experience at Lower node (N3, N5) is critical for this position.