Senior PD Engineer: Synthesis & STA
This is the employer's own posting, not a copy on a job board.
What we know
Is it still open?
Confirmed still open
Last checked 1d ago — checked against the employer's own applicant tracking system, which is the company answering directly.
We re-read the employer's own applicant tracking system and the posting was still there. That is the company answering directly.
How old is it?
Posted 39d ago
The date the source published, not the day we noticed it (2026-08-06). Last seen at its source 1h ago.
Is it remote?
Bangalore INDIA Hybrid / Remote
That is the location the employer filed this posting under. Quoted as written — we do not re-word the source's own location.
Who may apply?
India
The description agrees: it names India.
What the ad says
…Location: Bangalore INDIA Hybrid / Remote Role Overview We are seeking…
Pay not stated
Similar roles pay $6,750–7,250/mo
Middle 50% of 9 listings that do state pay — Engineering · all levels · India · USD/month. This employer has published no salary; this is what comparable listings we hold disclose, never converted between currencies or periods. How this is calculated.
Skills named in the ad
Recognised terms only, from a fixed vocabulary — this is what CV matching compares against.
Carried by 1 source
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greenhouse employer's own board first seen 11d ago · last seen 1h ago
The listing
- Synthesis Ownership: Drive and own the complete logic synthesis process for all designated blocks and sub-chips, ensuring optimal area, power, and performance metrics.
- Quality Signoff: Define, execute, and monitor rigorous sanity checks to achieve a high-quality, pristine Synthesis Signoff.
- RTL Collaboration: Work closely with RTL design engineers to ensure the delivery of a clean, fully linted netlist prior to handoff.
- Frequency & LOL Optimization: Deep dive into timing paths to ensure Levels of Logic (LOL) are strictly controlled and aligned with high-frequency target requirements.
- Micro-architecture Guidance: Go beyond reporting LOL violations; provide actionable RTL coding guidelines, structural recommendations, and micro-architecture inputs to help designers transform their code into a superior, synthesis-friendly netlist.
- Role Expansion: Progressively take on responsibilities in physical implementation adjacencies, actively participating in PNR execution, Static Timing Analysis (STA), and full-chip timing convergence.
- Experience: 5 to 8 years of proven experience in ASIC/SoC Logic Synthesis and Static Timing Analysis.
- EDA Tools Expertise: Hands-on experience with industry-standard synthesis tools, with a strong preference for Cadence Genus. Proficiency with STA signoff tools (e.g., Tempus, PrimeTime) is also required.
- Timing & STA: Strong foundational knowledge of STA, timing constraints (SDC), delay calculation, and multi-mode multi-corner (MMMC) analysis.
- RTL & Logic Fundamentals: Deep understanding of Verilog/SystemVerilog, digital logic design, and RTL linting/CDC tools.
- Netlist Optimization: Proven ability to analyze datapath architectures, identify logic bottlenecks, and recommend specific RTL changes to reduce logic depth.
- Scripting/Automation: Proficiency in Tcl, Python, or Perl for developing and maintaining synthesis flow automation and customized reporting scripts.
- Cross-Functional Communication: Excellent analytical and communication skills to effectively negotiate solutions between RTL and Physical Design teams.
- Prior exposure to Place and Route (PNR) flows (e.g., Innovus, ICC2) and a solid understanding of how synthesis decisions impact physical placement and routing congestion.
- Experience with Formal Verification / Logic Equivalence Checking (LEC/Formality).
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Knowledge of advanced technology nodes (e.g., 5nm, 3nm) and their specific synthesis/timing challenges.