Staff/Senior Staff Physical Design Engineer (Technical Lead)
This is the employer's own posting, not a copy on a job board.
What we know
Is it still open?
Confirmed still open
Last checked 15h ago — checked against the employer's own applicant tracking system, which is the company answering directly.
We re-read the employer's own applicant tracking system and the posting was still there. That is the company answering directly.
How old is it?
Posted 206d ago
The date the source published, not the day we noticed it (2026-02-20). Last seen at its source 1h ago.
Is it remote?
Bangalore or Remote in India
That is the location the employer filed this posting under. Quoted as written — we do not re-word the source's own location.
Who may apply?
India
The description agrees: it names India.
What the ad says
…Location: Bangalore Hybrid/Remote or Remote in India The Role We are s…
Pay not stated
Similar roles pay $6,750–7,250/mo
Middle 50% of 9 listings that do state pay — Engineering · all levels · India · USD/month. This employer has published no salary; this is what comparable listings we hold disclose, never converted between currencies or periods. How this is calculated.
Skills named in the ad
Recognised terms only, from a fixed vocabulary — this is what CV matching compares against.
Carried by 1 source
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greenhouse employer's own board first seen 11d ago · last seen 1h ago
The listing
EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.
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Technical Leadership: Lead a small team of PD engineers, providing technical direction, workload management, and architectural oversight for a sub-chip or partition.
- Complex Block/Sub-chip Ownership: Take personal hands-on ownership of the most critical, high-congestion, or timing-critical blocks in the design.
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Timing & PPA Strategy: Act as the primary architect for PD convergence. Derive and implement custom "PPA recipes" that go beyond standard vendor flows to meet aggressive targets.
- Advanced Automation: Drive efficiency across the team by developing sophisticated Tcl and Python scripts for flow automation, data mining, and sign-off verification.
- Stakeholder Management: Build strong rapport with RTL, DFT, and Synthesis teams. Effectively communicate risks and push for "left-shift" optimizations to safeguard the project schedule.
- Sign-off Accountability: Ensure the sub-chip meets all gold-standard sign-off criteria, including STA, EM/IR (Voltus/Apache), and Physical Verification (Pegasus/Calibre).
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Category
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Requirement
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Experience
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Staff 8-10 years
Senior Staff 11-13 years
PD experience with a proven track record of multiple successful lead-level tape-outs. |
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Tool Mastery
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Expert-level proficiency in Cadence Innovus/Tempus
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Timing Convergence
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Deep expertise in Static Timing Analysis (STA), including complex clocking, multi-corner sign-off, and crosstalk closure.
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PPA Optimization
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Demonstrated ability to squeeze performance out of advanced nodes (7nm, 5nm, or below) via custom floorplanning, CTS strategies and other convergence approaches.
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Automation
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Advanced scripting in Tcl and Python to build scalable, repeatable design methodologies.
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- High Workability & Assertiveness: You are a proactive communicator who can hold ground on technical requirements while remaining collaborative and solution-oriented.
- Analytical Problem Solver: You don't just identify violations; you analyze the "why" and derive a systemic fix that prevents the issue from recurring.
- Driven & Versatile: You possess the "Senior Staff" mindset—ready to jump into any part of the flow (from floorplan to GDSII) to unblock the team and meet the schedule.
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Mentorship: Passionate about raising the technical bar for the engineers reporting to you.